Analog to digital converters (ADC) provide the interface between the analog world and digital systems. While digital signal processing becomes increasingly popular, many traditional analog functional blocks have been replaced by digital blocks. Due to extensive use of analog and mixed analog digital circuitry, ADC often appear to be the bottleneck in signal processing operations. Various types of ADCs exist, such as delta sigma modulator ADCs or successive approximation register (SAR) ADCs.
In the successive approximation method, the data bits of the digital output signal are successively determined one after the other in a successive approximation step. Generally, the analog-to-digital converter is provided with a comparator, a digital-to-analog converter (DAC), a successive approximation register (SAR), and a logic circuit. The successive approximation method first involves setting the most significant bit (MSB) and then using the digital analog converter (DAC) to ascertain the associated value of an analog voltage. If the input analog voltage to be converted is higher than the ascertained output analog voltage of the digital analog converter (DAC), then the set-bit remains set and, in the converse case, it is reset. The next less significant bit is then set and the digital analog converter (DAC) is used to generate the associated analog output voltage from the corresponding digital value. The analog output voltage formed is then compared with the analog input voltage that is to be converted, and the comparator is used to decide whether or not the set-bit can remain set. The method is continued in this manner until all the bits of the binary coded digital analog converter have been ascertained successively.
The speed of the DAC and the comparator limits the conversion time of a successive approximation ADC. For example, an n-bit ADC must take n decisions for every conversion, and every decision must be as accurate as the final result of the conversion. The time for the comparator decision depends on the voltage step at the beginning of the comparison time. The recovery time increases for large voltage jumps. Therefore, if the design is changed so that the result is insensitive to small errors in the decisions with the highest voltage jumps, the conversion time can be improved. This leads to analog-to-digital converters with redundant codes.
Analog-to-digital converters with redundancy use codes with bases smaller than 2 (non binary). There are several digital codes for every input voltage, so small errors do not affect the conversion result. A DAC with a non-binary network is normally the key element of such an ADC. However, the major drawback of a non-binary DAC is poor matching and thus, minor linearity. The solution is to use the ubiquitous thermometer coded DAC which is fed by redundant preprocessed data. In such non-binary successive approximation analog-to-digital conversions, adding and subtracting operations are essential for processing the binary digits.
Therefore, at very high ADC frequencies (e.g. 430 MHz), it would not be feasible to start the adding and subtracting operation of a typical SAR ADC after the decision of a comparator. For example, a 14 bit addition needs about 1.3 ns in a 0.13 μm CMOS process.
An example of such a SAR ADC is illustrated in prior art FIG. 1, comprising a read-only-memory (ROM) 1, adding and subtracting means 3, a bus 5 and a decoder 7, a digital-to-analog matrix 9, a comparator 11, a pre-amplifier 13, a latch 15, a sample-&-hold block 17 and two registers 19 and 21.
Prior art FIG. 2 illustrates a SAR ADC comprising a ROM 23, an adder 25 and a subtractor 27 connected to a multiplexer 29 pre-processing the digital approximation values of which one is selected by a comparator 31 via the multiplexer 29. This parallel generation of digital values through an adder 25 and a subtractor 27 is known as 2-stage pipelining. The 2-stage pipelining SAR ADC illustrated in FIG. 2 further comprises a bus system 33, a decoder 35, a digital-to-analog matrix 37, a pre-amplifier 39, a latch 41, a sample-&-hold block 43 and a data register 45.
However, a time budget example for the operating sequence of the 2-stage pipelining SAR ADC (prior art FIG. 3) shows that the pre-amplifier is left with a time period of only t5=0.36 ns at an operation frequency of 35 MHz and a bit-length of n=12. Here, t5 is determined by subtracting the time needed for each part from the total time needed for the iteration cycle, e.g. t0=2.36 ns (iteration cycle), t1=0.7 ns (latch+driver), t2=0.3 ns (MUX+bus), t3=0.7 ns (decoder+driver) and t4=0.3 ns (DAC matrix), resulting in the time available for the Pre-amplifier to settle of t5=t0−t1−t2−t3−t4=0.36 ns.
For example, at a required amplification in the range of 200 the pre-amplifier would need at least double that time. In other words, the SAR ADC displayed in prior art FIG. 2 could not operate at the frequency suggested in the above example.